RTL Design
- Design Implementation at micro architecture level
- Performing lint
- Performing CDC & RDC
- Gate level Simulation
- Synthesis & Net list
- Performing GF library cells to TSMC compatible library cells
- RTL implementation on FPGA’s, Emulation build
Design Verification
- S.V based test bench creation
- UVM based Test bench creation
- UVM based RAL
- Assertions & Constant Random Verification
PCB Design
- schematic design services
- Layout Design Services
- Pre SI & Post SI design services
- Assembly design services
- Testing Hardware
Embedded S/W
- Board Support packages
- Device Drivers
Physical Design
- Analog CMOS Layout
- Digital CMOS Layout
- Performing Layout, Routing, DRC
PDK
- Net list generation for ASIC/SOC design
- Fabrication and tape out with TSMC
AI and robotics
- Implementation of ROS (Robotic operating systems), Implementation of ML/DL for speech processing, speech in recognition
- Object detection algorithms implementation for tracking and detection, classification on the GPUs and AI accelerators using Cuda, open GL, open CL
